3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
2015pp. 1–3
Citations Over TimeTop 10% of 2015 papers
Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup Jose, Bruce Xu, Daniel Wu, Didem Turker, H.A. Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Thang Pham, Yohan Frans, Ken Chang
Abstract
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.
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