Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs

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Abstract

This paper proposes a hybrid built-in self-test (BIST) approach for multi-port memory testing, featuring an algorithm with both a programmable portion and a hard-wired portion. The programmable portion solves a common problem encountered in programmable BIST with respect to detecting inter-port defects in multi-port memories, while the hard-wired portion can detect certain special memory faults that cannot be detected by the programmable portion. The hybrid approach resolves the large area overhead problem when programmable BIST is only used to implement memory test algorithms and provides flexibility of debugging defects by using the programmable portion algorithm. Experimental results have demonstrated the advantages of the proposed architecture.

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