Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing
2012pp. 1–3
Citations Over TimeTop 10% of 2012 papers
D. Ingerly, Ankur Agrawal, Ricardo Ascázubi, A. Blattner, Markus J. Buehler, V. Chikarmane, Bibhuti Bhusan Choudhury, F. Cinnor, Canay Ege, C. S. Ganpule, Timothy E. Glassman, R. Grover, P. Hentges, J. Hicks, Derick Jones, A. Kandas, Haseeb A. Khan, N. Lazo, K. S. Lee, H. Liu, Advait Madhavan, R.S. McFadden, T. Mule, D. Parsons, Prahalad M Parthangal, S. Rangaraj, D. Srinivas Rao, Joachim Roesler, A. Schmitz, Monika Sharma, Jin-Ho Shin, Y. Shusterman, N. Speer, Pramod Kumar Tiwari, G. Wang, P. Yashar, K. Mistry
Abstract
We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.
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