A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests

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Abstract

When functional tests are used for manufacturing testing, their quality for detecting manufacturing defects needs to be evaluated. Evaluating functional tests using a traditional gate-level fault simulation environment has several disadvantages. To alleviate them, we describe a functional level coverage metric for estimating gate-level fault coverage that has a high degree of correlation to gate-level coverage. We borrow concepts from simulation-based design verification by defining fault detection conditions as coverage objects and monitoring their occurrence, also called their hit counts, during RTL simulation. To reduce the simulation overhead, we abstract gate-level fault detection conditions to the architectural level. The resulting hit counts are converted to an estimated fault coverage using a formula. Experimental results are presented on three datapath modules in a high-performance microprocessor considering two applications: identification of functional tests with high gate-level coverage relative to other tests, and identification of modules or module functions that require additional functional tests

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