A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
2006pp. 58–65
Citations Over TimeTop 1% of 2006 papers
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Takenobu Suzuki, Kewal K. Saluja, Laung‐Terng Wang, K.S. Abdel-Hafez, K. Kinoshita
Abstract
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
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